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Strategic Partnership

HyperSilicon Co.,Ltd. and Bluespec. Inc. are Strategic partner for the promotion of the next generation technologies of Electronic System Level(ESL) Modeling, Design, Compiling, Simulation and Co-Emulator in China. HyperSilicon takes responsibility of marketing , sales and technical support on all tools of Bluespec.

About Bluespec.Inc.
Bluespec is the Synthesizable Modeling Company, with Bluespec, modes and test benches can be synthesized along with legacy IP to employ Emulator much earlier for modeling, verification and early software development, Bluespec makes Emulator much easier, more affordable, and deployable from concept to volume silicon
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Technology Overview
Based on eleven years of continued research at MIT and over eight years of commercial development at Bluespec. Inc. BSV’s patented, silicon-proven technology is built on four core elements:
Guarded atomic transactions
Control-adaptive parameterization
Modern high-level language facilities
Support of standard mainstream technologies
Application
Architectural models
Synthesizable test benches
Synthesizable transactors
Executable specs
Production RTL
Bluespec Customer List
"E-BOOK" and “software”please go to "Download Center"
Reference design with BSV please go to "Download Center"
"Bluespec University Plan" please contact to hypersilicon@hypersilicon.com
Support please go to"http://www.bluespec.com"
Bluespec Products
Bluespec BSC can be used alone or it can input Verilog & C/C++

1. Imported Verilog is passed through to the Verilog output
2. Imported C/C++ is executed in the Bluesim simulator

BSC Compiles Blespec BSV to synthesizable Verilog or to a Bluesim executable
Bluesim provides fast cycle-accurate simulation for BSV and C/C++ codesEmulator App brings low cost Emulator to 3rd party FPGA boards
More detail information please go to " http://www.bluespec.com/"
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Synthesizable Modeling Kit components and Features
Bluespec System Verilog(BSV)Language
High-level-comparable to C++/Java
Synthesizable-no non-synthesizable language constructs
General purpose-handle all kinds of IP (not just data path)
Scalable-use for modules, subsystems, and full chips
Seamless-abstract models to production silicon IP
Power Concurrency modeling and implementation
Atomic transactions and interface methods
Scalable across shared resources and module boundaries
Powerful structural modeling and implementation
Polymorphic high-level types
Powerful parameterization
Static checking and formal semantics
Advanced clock management
Extensive libraries and utilities to accelerate coding
Hundreds of modules and functions for data types, memory, math,aggregation, and connectivity(TLM,AXI,OCP…)
PAClib generator for pipelined 
data path architectures
StmtFSM generator for complex, concurrent, nested finite state machines
Interoperable
Import existing RTL
import into existing RTL
Import C/C++ /import into 
SystemC(simulation only)
Bluespec Compiler(BSC)
Correct-by-construction complex control logic from atomic transactions
Outputs synthesizable Verilog from BSV
Plugs seamlessly and incrementally into existing flows
Bluespec Synthesizable Modeling Advantages
Superior concurrency model of atomic transactional rules eliminated errors from explicit management of threads and shared resources
100% synthesizability eliminates wasted time and effort spent coding around non-synthesizable subsets
Control adaptive compilation automatically generates control logic. Speeding uo design iteration 10X or more
Powerful language constructs enable efficient and transparent coding complex hardware architectures
100% general purpose language works for data-path, control, interconnect, test bench, transactors…
Proven path to production quality RTL eliminates the model-to-RTL implementation gap
Desktop Emulator-semu

Semu simplifies FPGA-based emulation along with debug visibility and control,providing dynamic state visibility and hardware breakpoint capability without re-synthesis while providing connectivity between the host and the DUT.

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Semu Breaks the function verification bottleneck with easy-to-use Emulator
Are simulators too slow to fully verify today’s complex IP block and subsystems?
Are corner cases too difficult to reach?
Are running real data and full regressions next to impossible ?
While Emulator and FPGAs promise high-speeds, they are too expensive& difficult-to-us.
Semu breaks the functional verification bottleneck by delivering the high-speed of FPGA-based Emulator, without compromising debug visibility and control
Semu providers affordable, high-speed desktop Emulator
Semu software integrates with standard, low-cost Xilinx FPGA Development Boards to deliver affordable, desktop Emulator, Semu support up to 20M* ASIC gate and up to 50Mhz for high-speed function verification of complex IP blocks and subsystems.
Semu deploys in hours, not weeks or months

Is it too hard to get a design successfully into an FPGA? Too formidable to then connect a test bench to it? How many weeks, even months, are required to bring-up a design on an FPGA board?
Semu is simple, Install software on your Linux PC, connect your Xilinx FPGA board and go! Easily import your design with semu, quickly configure your project and automatically integrate the design into FPGA Emulator, And, semu provides a C API to your design to make it easy to connect your test benches and models. Semu seamlessly handles everything else to connect to your design-automatically building the hardware and software transactors and the PCIe-based co-Emulator infrastructure .semu enables you to bring-up your first design in less than a day ,versus months of lost effort, trying homegrown methods.

Semu enable debug iterations in minutes, not hours
Does your FPGA-based debug require design ” re-instrumentation and re-synthesis’ for each iteration? Does that take hours or days? Does isolating and fixing bugs lapse into days>Semu lets you dynamically debug your design without “re-instrumenting and re-synthesizing” Semu provides dynamic visibility, and hardware breakpoint capability, against 100% of the register state for your design at any time. therefore with semu, debug iterations happen in minutes, not days.
Semu Flow
Flow
Verification IP(VIP) Templates
VIP Picture
More Verification IP(VIP) templates please go to "Download Center"
             
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