Memory Medols

SmartDV develops Memory Models, leveraging their rich experience in ASIC / SoC design verification and capabilities on high-level verification languages (HVLs). Their Memory Models are configurable, reusable plug-and-play verification solutions for standard interfaces based on HVL. SmartDV currently supports SystemVerilog, Vera, SystemC, Specman E and Verilog. All their Memory Models are supported natively in SystemVerilog VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env.

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