SimXL - Emulation Models

SmartDV develops Synthesizable Transactors(Emulator Models), leveraging their rich experience in ASIC / SoC design verification and capabilities on high-level verification languages (HVLs) and Emulators, Which can run in Veloce/Palladium/Zebu and any custom FPGA platform. Their Synthesizable Transactors(Emulator Models) are configurable, reusable plug-and-play verification solutions for standard interfaces based on HVL. SmartDV currently supports Verilog for Synthesizable Transactors with UVM/OVM/SystemVerilog/SystemC/C interface for controlling Synthesizable Transactors(Emulator Models). All Synthesizable Transactors(Emulator Models) have been developed to have same functionality as their VIP's with good performance.

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