DIGITAL CORE DESIGN

More than 500 000 000 electronic devices around the globe based on DCD’s IP Cores. Join us!! Digital Core Design is a leading Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house. The company was founded in 1999 and thanks to in-depth specialization and innovative approach we have introduced more than 70 different architectures. Among them you can find e.g. World’s Fastest 8051 CPU, World’s Smallest 8051 CPU, silicon proven and royalty-free 32-bit CPU.

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  • 产品特征

Cryptography

 

The DCRP1A - CryptOne IP is a 100% safe cryptographic system

  • CryptOne constant time algorithms:

        Modular exponentiation

        Parallel modular exponentiation CRT

        ECDSA sign/verify

        ECDH

        Elliptic curve point multiplication

        Modular multiplicative inverse

        GCD

        Modular reduction

        Multiplication

        Division

  • Cryptographic algorithm applications:

        ECDSA, ECDH

        RSA key generation

        RSA Sign/Verify/Encrypt/Decrypt

        Diffie-Hellman schemes

        Miller-Rabin Primality check

  • System applications:

        Client-server communication

        Sensor networks

        SSL/TLS stacks

        IoT devices

        Embedded security/ID devices

  • AMBA AHB, AXI4, APB interface ready
  • Rapid & easy development with delivered API
  • Patent pending architecture
  • Algorithms resistant against SPA and timing attacks
  • CryptOne elliptic curves with native support:

        NIST P-192

        NIST P-224

        NIST P-256

        NIST P-384

        Koblitz P-192

        Koblitz P-256

        Koblitz P-384

        Brainpool P-256

        Brainpool P-384

        Brainpool P-512

        Other/custom curves optional support

  • Software support:

        OpenSSL engine

        MbedTLS port

        OS independent crypto library

 

The DSHA2-256 - a universal solution which accelerates SHA2-256 hash with HMAC mode.

KEY FEATURES

  • FIPS PUB 180-4 compliant SHA2-256 function
  • RFC 2104 compliant HMAC mode native support
  • SHA2 224 and 256 bit modes support
  • Secure storage for precomputed HMAC keys
  • Hash/HMAC context swapping
  • Internal, automatic padding module
  • Binary message resolution support
  • Flexible data read/write modes
  • AMBA AHB, AXI4, APB interface ready
  • Software support:

        Software driver with OpenSSL/MbedTLS interface ready

  • Applications

        Digital signature

        Data integrity

        Key derivation

        TLS/SSH/PGP IPsec communication

 

CPUs

 

D32PRO

The D32PRO is a royalty-free, silicon proven, high performance soft core of a single-chip 32-bit embedded controller, with Floating Point Coprocessor.

KEY FEATURES

  • Configurable 32-bit Harvard architecture
  • Performance up to 1.52 / 2.67 DMIPS/MHz and 2.59 CoreMarks/MHz
  • Small footprint starting at 10.6k/6.8k ASIC gates
  • Very high clock frequency up to 1 GHz in modern ASIC technologies
  • Fifteen 32-bit general Purpose registers
  • ASIC Silicon proven architecture
  • Up to 256 MB of Code Space with encrypted bootloader
  • Up to 256 MB of Data Space
  • Built-in configurable Floating Point co-processor using dedicated instructions
  • Configurable 32-bit hardware multiplier
  • Configurable 32-bit hardware divider
  • Configurable 32-bit hardware shifter
  • Low power consumption by Advanced Power Management Unit

        Advanced Power management mode

        Switchback feature

        Stop mode

  • Configurable Interrupt Controller

        Non Maskable Interrupt

        Up to 16 priority levels

        Up to 32 external interrupt sources

  • System clock controller supporting

        Phase Locked Loops (PLL)

        external clock generator

        on-chip clock oscillator

  • DoCD™ on-chip debug unit
    • Processor execution control
      • Run, Halt
      • Step into instruction
      • Skip instruction
    • Read-write all processor contents
      • System Space
      • Program Memory Space
      • Data Memory Space
      • Peripherals Space
    • Code execution breakpoints
      • up to eight real-time PC breakpoints
      • unlimited number of real-time OPCODE breakpoints
    • Hardware execution watchpoints at
      • Data Memory Space
      • Program Memory Space
      • Peripherals Space
      • System Space
    • Hardware watchpoints activated at a certain
      • address by any write into any Space
      • address by any read from Space
      • address by write into space a required data
      • address by read from space a required data
    • Hardware watchpoint windows activated at a certain
      • Start/stop address by any write into any Space
      • Start/stop address by any read from Space
      • Start/stop address by write into space a required data
      • Start/stop address by read from space a required data
    • 2-wire high-speed communication interface
  • Ultimate dense code
  • Great variety of peripherals
  • AHB-Lite interface ready
  • Rapid & easy development with ready to use tools
  • Customization friendly with GUI
  • Patent pending architecture
  • Royalty-free

  

DQ80251

The DQ80251 is a revolutionary Quad-Pipelined ultra high performance, speed optimized soft core of a 16-bit/32-bit embedded microcontroller. The core is fully configurable – this allows an easy selection of features and peripherals, in order to create a dedicated system. It was designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced power management unit – the PMU. The DQ80251 utilizes 20 years of DCD’s know-how with triumphant 8051 architectures. The core is 100% binary-compatible with industry standard 16-bit 80C251 and 8-bit 80C51 microcontrollers. There are two working modes of the DQ80251:

  • BINARY (where the original 80C51 compiled code is executed), and
  • SOURCE (a native 80C251 mode using all DQ80251 performance).

KEY FEATURES

  • 100% binary compatible with industry standard 80C251, implementing BINARY and SOURCE modes
  • Single clock period per most of instructions
  • Quad-Pipelined architecture enables to run 75 times faster than the original 80C51 and 6 times faster, than the 80C251 at the same frequency
  • Up to 75.08 VAX MIPS ratio
  • Up to 8M bytes of Program Memory
  • Up to 32k bytes of internal (on-chip) Data Memory
  • Up to 8M bytes of external (off-chip) Data Memory
  • Up to 16 MB of total memory space for CODE and DATA
  • 32k bytes of extended stack space
  • User programmable Program Memory Wait States solution – for wide range of memories’ speed
  • User programmable Extended Data Memory Wait States solution – for wide range of memories’ speed
  • De-multiplexed Address/Data bus, to allow easy connection to memory
  • Full Program Memory writes
  • Interface for additional Special Function Registers
  • Fully synthesizable
  • Static synchronous design
  • No internal tri-states
  • Scan test ready
  • USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available