Tools for easily bring up, Shorten time to prototype

Provide intelligent tools for easily bring up and to shorten the time of RTL to bitsream. Such as hsSynth, the high speed parallel compile solution, speeds up the synthesis process multiple times. hsPar, the semi-auto partition tool, provides a high performance partition solution for multi-FPGA board.

Rich Connectivity and 100+ Daughter Cards

Rich Connectivity is built in VeriTiger-E4000Ts for 100+ ready daughter cards provided by HyperSilicon®. Flexible interfaces deliver high flexibility for clocking, debug and host interface, hsDman, the daughter card management software researched and developmented by HyperSilicon®, can effectively monitor and manage abundant daughter cards.

High performance, Fast running speed

Provide high performance interfaces for data transmission between host and VeriTigers and debug signal capture. GTH transceivers run up to 16.3Gbps for the interconnect of FPGAs and are ideal for high-performance IP and SoC prototyping. VeriTiger®-E4000T runs up to 100 MHz for advanced IC design.

Large capacity, High scalable

Single FPGA system VeriTiger®-E4000T provides 26 million estimated ASIC gates and 4 FPGAs system VeriTiger®-QE4000T provides nearly 100 million ASIC gates, we also provide interconnect and partition solutions for multi-QE4000T deployed in rack or cabinet for larger design.

Key Parameter

Product Model	Capacity	FPGA RAM	DSP Slices	User IOs	Memory Support
VeriTiger®-QE4000T	~ 104M ASIC Gate	354.4Mb	11520	4112	DDR4*12,DDR3*12
VeriTiger®-DE4000T	~ 52M ASIC Gate	177.2Mb	5760	2056	DDR4*6/DDR3*6
VeriTiger®-E4000T	~ 26M ASIC Gate	88.6Mb	2880	1028	DDR4*3/DDR3*3

功能标签

子卡是功能验证的重要辅助工具，能够有力增强验证扩展性。亚科鸿禹提供100多种即拿即用功能子卡资源，并提供经过众多开发项目充分验证的成熟解决方案。同时随着SoC/ASIC设计验证的需求不断多样化，更多类型的子卡需求不断涌现，亚科鸿禹专业研发团队可根据验证项目需求提供快速高效的子卡定制服务。