HyperEmu Emulator--For VLSI Verification
HyperSilicon Co., Ltd. has been deeply involved in the research and development of digital IC design verification EDA tools and their application in projects for over a decade. This commitment has amassed services for more than 500 cutting-edge digital development teams. HyperEmu, also known as the HyperSilicon Higher Performance Emulator, leverages profound application experience and cutting-edge innovations in digital IC development methodology. It adopts an innovative hardware architecture and establishes a high-performance verification software ecosystem. HyperEmu supports flexible capacity expansion, automated design partitioning, high-performance execution and debugging. This satisfaction of comprehensive scenario application requirements in verification significantly expedites the early market launch of the next generation of chips.
Key Benefits
Large-scale Capacity
Offering board-level, rack-level, and cabinet-level configurations, the system supports flexible capacity expansion and achieves ultra-large-scale verification capabilities.
Higher Performance
Achieves multi-MHz running and debugging performance in ultra-large-scale verification scenarios, significantly accelerating both verification and design iteration.
Easier Debugging
Equipped with synchronous support for proprietary and universal waveform data formats, it enables full visibility and flexible, efficient signal tracking and debugging.
Acceleration Modes
Supports acceleration modes such as TBA and ICE, and enables Hybrid emulation, significantly shifting the development cycle to the left.
Full-Scenario
Simplified and streamlined to meet a comprehensive range of verification needs, including early architectural validation, module functional verification, system-level verification, regression testing, and power consumption analysis.
Highlight Advantages
Capacity：
Based on the high-performance, high-capacity XCVU19P FPGA with abundant interfaces and expandability. A single board supports 200 million ASIC gates, with a full cabinet configuration, support for up to 3 billion gates is achieved. Through cabinet-to-cabinet cascading, verification capability equivalent to 15 billion logic gates can be realized.
Performance：
Achieves over 10MHz in running and debugging performance, with typical performance exceeding 1MHz.
Design language and input support：
Supports mainstream RTL hardware description languages such as Verilog, VHDL, System Verilog, and EDIF netlists. Additionally, it supports a variety of testbenches including C, C++, SystemC, and UVM verification methodologies.
Compilation：
Supports full automatic compilation, manual compilation, and distributed compilation. It also supports multi-user operations, with a maximum of 400 users online simultaneously.
Acceleration mode support：
Supports Transaction-Based Acceleration and In-Circuit Emulation acceleration modes. Additionally, it supports Hybrid emulation in conjunction with virtual platforms, which notably shifts the development cycle to the left.
Transactor provision：
This furnishes a range of transactors tailored for swift software-hardware synergy in TBA acceleration mode, addressing mainstream verification needs such as APB3, AXI4, AHB3, JTAG, UART, GPIO, I2C, USB3/2, PCIE5/4/3. Continuous development and refinement are underway to enhance its capabilities.
Speed bridge provision：
This is utilized for verifying peripheral interfaces in DUT and can be interconnected with external real interfaces. It currently supports JTAG, UART, I2S, I2C, PCIE Gen5/4/3 x1/x4/x8/x16 EP&RC, SATA3/2/1, Ethernet 10M/100M/1000M/1G/10G/25G/40G/50G/100G, USB3/2 Host/Slave, Multimedia, among others.
Synthesizable model support：
Continuously develops synthesizable alternative models that emulate the behavior of Memory modules in DUTs, enabling rapid and comprehensive synthesis from system-level design to FPGA. Currently supports SPI, NAND, DDR2/3/4/5, LPDDR2/3/4/5, HMC, HBM2E, eMMC, etc.
Debugging capabilities：
Our proprietary high-compression waveform file format (HSDB) and the corresponding viewing and debugging tools (which also support VCD and FSDB file formats) enable efficient and rapid viewing, precise analysis, and flexible debugging of large-scale waveform data. This supports full visibility of 100% of signals at the system level, allows for the flexible setting of complex trigger conditions (Trigger), and facilitates Memory backdoor operations.
Debugging methods：
Support common debugging techniques such as Probe, Readback, Force-Release, Trigger, and Checkpoint, allowing for the flexible setting of debugging strategies. It also supports Memory Backdoor, significantly enhancing the speed and efficiency of design verification and debugging.
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