Thomas Yan, our CEO, was interviewed by Wuxi Daily as a representative of high-tech company in Xishan district.

VeriTiger-QV19P--Based on Xilinx VU19P FPGAs, Can be used as prototyping system and emulator!

VeriTiger®-QE4000T--delivers higher debug productivity for designs of various sizes, applications and stages.

Hybrid Emulation--a great assistant to enable early architecture optimization, software development and RTL verification.

hsTrace deep depug tool--hsTrace stores the waveform data into an external DDR instead of occupying FPGA RAM.

hsSynth parallel synthesis solution--delivers multiple speed up for Large-scale digital design synthesis.

“Experience of Verification” Series Webinars No.2：HAV tools accelerate digital design verification.

“Experience of Verification” Series Webinars No.1：Emulation plays an important role in the process of digital design verification.

What happened at HyperSilicon’s booth of ICCAD 2021--We released VeriTiger-V19P Series, our latest prototyping system.

HDL Creator™（Blue Pearl Software, Inc）--a full-featured source code editor that provides real-time syntax and style checking during HDL code development.

Analyze RTL™（Blue Pearl Software, Inc）--combines the ease-of-use methodology and extensive analysis of super-lint tools with the power of formal verification into a single high performance, high capacity design checking solution.

CDC Analysis（Blue Pearl Software, Inc）--comes with a complete set of CDC analyses, an Advanced Clock Environment (ACE) for solving the iterative and reactive CDC setup problem, and a comprehensive set of debugging tools.

Management Dashboard（Blue Pearl Software, Inc）--delivers real-time visibility to ASIC, FPGA and IP RTL design rule and CDC checks to better assess schedules, risk and overall design quality.

SDC Generation（Blue Pearl Software, Inc）--offers a way to automate false path generation that can be run after design changes, limits the number of exceptions generated, reads in critical paths information and accepts multiple formats.

ACE（Blue Pearl Software, Inc）--offers the capability to visualize clocks and asynchronous clock domain crossings in RTL designs to help users analyze their design for CDC metastability.

The ceremony of Relocating our headquarters to Wuxi and founding "The Jiangnang EDA Industry-University-Research Collaboration Alliance"